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Xilinx ChipScope Tutorial

Posted by Omkar on March 24, 2010

Using the ChipScope Pro for Testing HDL Designs on FPGAs


Simulation based method is widely used for debugging the FPGA design on computers. Time required for simulating complex design for all possible test cases becomes prohibitively large and simulation approach fails. For rapid testing, such designs can be loaded on to the target FPGAs and tested by applying test inputs and directly observing their outputs. As the complexity of the design under test increases, so does the impracticality of attaching test equipment probes to these devices under test. The ChipScope Pro tools integrate key logic analyzer and other test and measurement hardware components with the target design inside the FPGA. Computer based software tool communicate with these hardware components and provide a designer robust logic analyzer solution.

In this tutorial we will use simple UP counter design and test it using ChipScope.

You can download the PDF file of this tutorial from here.

NOTE: For more detailed information on various settings and parameters of ChipScope Pro, refer to ‘ChipScope Pro 10.1 Software and Cores User Guide’.

Couter Design:

Create a new project in the Xilinx ISE and paste the following counter code in top module (cntr.v):

module cntr(
input rst,
input clk,
output [3:0] count

reg [25:0] cnt;
assign count[3:0] = cnt[25:22];

always @(posedge clk) begin
    cnt <= 0;
    cnt <= cnt + 1;

To assign the constraints to the design, create new file named ‘cntr.ucf’ and add it to ISE project. Paste following constrains in ‘cntr.ucf’ file. These constraints are applicable for XUP-V2P Development board.

NET “count<0>” LOC = AC4;
NET “count<1>” LOC = AC3;
NET “count<2>” LOC = AA6;
NET “count<3>” LOC = AA5;
NET “clk” LOC = AJ15;
NET “rst” LOC = AG5;

These constraints connect the ‘rst’ signal to ENTER button on the development board. Output nets are connected to on board LEDs.

Configuring the logic analyzer core:

In order to test the counter design we have to configure and insert the logic analyzer core in our design. Follow these steps:

· In the ‘Sources’ view right click on the top module (cntr.v) and select ‘New Source’.


· In the ‘New Source Wizard’ window, select ‘ChipScope Definition and Connection File’ and specify the filename as ‘debug’. Click ‘Next’.


· Now we have to associate this debug.cdc file with our desired top module. Thus select ‘cntr’ from list of the modules. If there are multiple modules shown, select the one which you wish to test. Click ‘Next’ and then click ‘Finish’.


Note that ‘debug.cdc’ file has been added to your ‘Sources’ list and is listed below the selected top module (cntr).


· Double click on ‘debug.cdc’ to launch the ChipScope Pro Core Inserter application. This application will integrate the logic analyzer core into our counter design. Do not alter any settings on the first screen. Click ‘Next’.


· To observe any signal, we have to specify the trigger. Logic analyzer core will start capturing the desired signal upon activation of trigger signal. In this example we want to monitor the counter’s counting action as soon as ‘rst’ signal is deactivated. So we will create two trigger ports. One port will be ‘rst’ signal and another port will be counter’s eight least significant bits.

Set ‘Number of trigger ports’ to 2.

In ‘TRIG0’ frame set ‘Trigger Width’ as 1 (since ‘rst’ is one bit signal).

In ‘TRIG1’ frame set ‘Trigger Width’ as 8 (as we want to observe counter’s 8 least significant bits).


Click ‘Next’.

· Now in this window we will specify capture parameters. We want to use our trigger ports as data ports which will be recorded by logic analyzer. We also want to sample data on rising clock edge.

In ‘Sample On’ list select ‘Rising’.

Set Number of samples to be recorded by changing ‘Data Depth’ to 1024 samples. This will record 1024 samples from the trigger event. You can at the most record 16K samples.

Select both check boxes in ‘Trigger Ports Used As Data’ frame.


Click ‘Next’.

· Now we will specify which signal(s) to be used as Clock and Trigger.

Click on ‘Modify Connections’.


· Select the ‘Clock signals’ Pane, then select ‘clk_BUFG’ signal from the left hand side list and then click on ‘Make Connection’. This will add ‘clk’ signal as the clock signal for logic analyzer.


· Now select ‘Trigger/Data signals’ pane. Select ‘TP0’ and connect ‘rst_IBUF’ signal to CH0 channel.


· Similarly click on ‘TP1’ pane and add connect counter’s lowe eight bits to eight channels.


Click ‘OK’ once you finish making connections.

· Now in the main window click on ‘Return to Project Navigator’. It will ask for saving the project, click ‘Yes’.


Now we are ready to compile the entire counter design along with the logic analyzer core.

· In the ISE, select top level module ‘cntr’ and in the ‘Processes’ pane double click on ‘Analyze Design Using ChipScope’. This will start the process to synthesize combined unit consisting of design under test (in this case counter) and the ChipScope cores.


Debugging the design using ChipScope Analyzer tool:


Once the synthesis gets over, ISE will launch the Analyzer tool. Make sure that FPGA board is connected to PC.

· Once the analyzer tool is running, click on ‘Initialize JTAG Chain’ clip_image028 icon located at the top right corner of the window. This will initialize the JTAG chain and identify the devices found in the chain. A dialog box will appear showing the devices discovered. Click ‘OK’.


· Now select the FPGA device from the JTAG chain, right click and then select ‘Configure’ to specify the configuration bit stream file.


· Select the bit stream file ‘cntr.bit’ from the bit stream folder. Then click ‘OK’.


· IMPORTANT: After clicking ‘OK’, tool will load the bit stream file into FPGA and check the availability of debugging cores. If debugging core is found tool will show ‘INFO: Found 1 Core Unit in the JTAG device Chain.’ Message in status window.

If you see ‘Found 0 Core …’ message instead, then either you have selected wrong bit stream file or something has gone wrong in one of the previous steps and debugging core has not been inserted properly into the design.

If everything is fine then you will see options for Logic Analyzer core inserted in our design. Now double click on the ‘Trigger Setup’ element to launch trigger setup window. And for trigger port 0 (i.e. ‘rst’ signal) specify the trigger Value 0.


This will make logic analyzer to trigger as soon as ‘rst’ become zero and record 1024 samples on successive clock edges. Note that trigger signals are sampled on rising clock edge.

Double click on ‘Waveform’ element to see the waveform.

· Now everything is ready. To apply the settings and ARM the trigger click on clip_image038 button. After that press the ‘Down’ button on the development board to release the ‘rst’ signal. This will trigger the logic analyzer. Once 1024 samples are recorded, this data will be transferred to PC and will be displayed in the waveform window.


Final data is uploaded on PC and displayed in waveform window.


NOTE: To see the names of the trigger ports, you can import the ‘debug.cdc’ file in analyzer tool. Click on File>Import and then select ‘debug.cdc’

NOTE: For more detailed information on various settings and parameters of ChipScope Pro, refer to ‘ChipScope Pro 10.1 Software and Cores User Guide’.

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28 Responses to “Xilinx ChipScope Tutorial”

  1. nix said

    Hi I am using a Virtex 7 board and performing a 64 bit ripple carry addition. Can any one help me how do I use chipscope along with this program of mine. I cannot assign UCF s to inputs or outputs I think as there will be 129 inputs for the 64 bit additions between a and b and the carry and 65 outputs for the sum and carry out. How am I supposed to trigger the cores and not use UCF and check the working on Chip Scope using FPGA


  2. mahi said

    i want to see the out put of my adc on chip scope.I have clk2 as a divided clock which i am using as a clock to adc and i hav 10 bit signal as output.I am ot getting which signal to be connected to trigger.I have connected clk2_buf to clk port and my signal to trigger and set the data port same as trigger but i am not getting the output waveforn ..Can me please help me with this.


  3. Mohan said

    sir i have 2 problems in spartan 3e using xilinx 10.1
    1. I cant change the trigger width
    2. After press play button it’ll take more time to upload waveform and the sample %ge is at 0 only.


  4. satish said

    for the below comment……………..
    It is not coming as clock signal,it is coming always high signal…….


    • Omkar said

      You cannot see the sampling clock in the chipscope. If you wish to see the clock signal itself, then, use the DCM to generate a clock signal which is twice (or even multiple) of the frequency of clock signal you want to observe. Then use this signal as a chipscope clock. You cannot measure time period from chipscope directly. Each time sample in the chipscope corresponds to one time period of the chipscope clock.


  5. satish said

    I tried to see input clk in chip-scope pro wave window,but it is coming as clock signal.Why? In chip-scope pro we are not able to see input clock signal??
    If we want to measure the clock frequency of input signal,how to measure the frequency?


  6. sumit darak said

    Excellent tutorial…Thanks a lot :)


  7. VHDL Student said



  8. Dave said

    …job well done!!


  9. mavi said

    Sir can i know deferent between .cdc file,.ucf file,.bit file?


  10. debolina said

    i am new in using chipscope pro, ur tutorial help me a lot.sir, can i watch the output of adc on spartan 3e using cipscopepro? if so,then how? plz help me giving ur suggestion and helpful document or link from where i will learnt thanks in advance sir.


  11. […] will give students quick hands on session for using xilinx's ChipScope Pro. Have a look at it : http://elecrom.wordpress.com/2010/03…cope-tutorial/ Comments/suggestions appreciated. Reply With Quote View […]


  12. Mukunda said

    The instructions are very clear!! Things worked at very first attempt.



  13. […] via Xilinx ChipScope Tutorial « Electronics – Tuts, tips and much more …. […]


  14. Ammar said

    So clear tutorial. Good job



  15. Ravi said

    Thanks a lot. Very well documented.


  16. ABDULLAH GILL said

    i m unable to see the waveform on SPARTAN 3E XC3S500 .


    • Omkar said

      please check your email.


      • ABDULLAH GILL said

        i m having difficulty in understanding why u have use trigger width of ‘8’ for the second trigger port? we may have used 6 as we had 6 signals to see.
        2nd problem is what the waveform is showing to us?it is a littel bit confusing?
        i hope u dont mind my silly questions .
        waiting for ur reply.
        GOD BLESS U


        • Omkar said

          - Yes, you can very well use the width of ‘6’. What I have shown is just one example. You can use suitable width according to your requirement. – What waveform chipscope shows ? Ans : Chipscope will sample the trigger ports on positive clock egde and show you the output waveform. Whatever you see at the output is basically plot of all such samples collected on the posedge of clk. It doesn’t show you what happens in-between two clock edges and it is not possible to do that using chipscope.


  17. abdullah said

    hi thanks for the tutorial its really very easy but i m having problem with it while capturing data on analyzer i m using spartan 3e starter kit.can u please help me out of this?


  18. Santosh said

    Thanks for the tutorial. Easy to follow and effective.


  19. Charles said

    Excellent tutorial. I am an independent contractor and I have a client who is interested using the Xilinx Virtix5 in an FPGA design. What tools do I need to input the the state diagram and input into a state machine. Is there a program that can take the state machine and cover it into a timing diagram?



    • Omkar said


      I didn’t get what exactly you want to do. There are some tools available which can realize the state machine from state diagram, but they are highly expensive.

      If you have complete description of the system and its state (or the state diagram), it is simple to implement the state machine directly by writing verilog code. Time required to do the implementation depends on the complexity of state diagram.


  20. Aaron said

    Excellent. Thanks.


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